SH7020 Datasheet, PDF (401/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

is selected, the SCI outputs data in synchronization with the input clock. Data are output from
the TxD pin in order from the LSB (bit 0) to the MSB (bit 7).
3. The SCI checks the TDRE bit when it outputs the MSB (bit 7). If TDRE is 0, the SCI loads
data from the TDR into the TSR, transmits the MSB, then begins serial transmission of the
next frame. If TDRE is 1, the SCI sets the TEND bit in the SSR to 1, transmits the MSB, then
holds the transmit data pin (TxD) in the MSB state. If the transmit-end interrupt enable bit
(TEIE) in the SCR is set to 1, a transmit-end interrupt (TEI) is requested at this time.
4. After the end of serial transmission, the SCK pin is held in the high state.
Transmit direction
Serial clock
Serial data
LSB
Bit 0 Bit 1
MSB
Bit 7 Bit 0 Bit 1
Bit 6 Bit 7
TDRE
TEND
TXI
request
TXI interrupt
handler writes
data in TDR and
clears TDRE to 0
TXI
request
1 frame
TEI
request
Figure 13.15 Example of SCI Transmit Operation
Transmitting and Receiving Data: SCI Initialization (clocked synchronous mode): Before
transmitting or receiving, software must clear the TE and RE bits to 0 in the serial control register
(SCR), then initialize the SCI as follows.
When changing the communication mode or format, always clear the TE and RE bits to 0 before
following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit
shift register (TSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and
ORER flags and receive data register (RDR), which retain their previous contents.
Figure 13.16 is a sample flowchart for initializing the SCI. The procedure for initializing the SCI
is listed below.
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