SH7020 Datasheet, PDF (421/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

• Bits 1 and 0 (PA0 mode (PA0MD1 and PA0MD0)): PA0MD1 and PA0MD0 select the
function of the PA0/CS4/TIOCA0 pin.
Bit 1: PA0MD1
0
1
Bit 0: PA0MD0
0
1
0
1
Function
Input/output (PA0)
Chip select output (CS4) (initial value)
ITU input capture/output compare (TIOCA0)
Reserved
14.3.3 Port B I/O Register (PBIOR)
The port B I/O register (PBIOR) is a 16-bit read/write register that selects input or output for
individual pins on a bit-by-bit basis. Bits PB15IOR–PB0IOR correspond to pins of port B. PBIOR
is enabled when the port B pins function as input/outputs (PB15–PB0), for ITU input capture and
output compare (TIOCA4, TIOCA3, TIOCA2, TIOCB4, TIOCB3, and TIOCB2), and as serial
clocks (SCK1, SCK0). For other functions, they are disabled. For port B pin functions PB15–PB0,
and TIOCA4, TIOCA3, TIOCA2, TIOCB4, TIOCB3, and TIOCB2, and SCK1/SCK0, a given pin
in port B is an output pin if its corresponding PBIOR bit is set to 1, and an input pin if the bit is
cleared to 0.
PBIOR is initialized to H'0000 by power-on resets; however, it is not initialized for manual resets,
standby mode, or sleep mode.
Bit: 15
14
13
12
11
10
9
8
Bit name: PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8
IOR
IOR
IOR
IOR
IOR
IOR
IOR
IOR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Bit name: PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
IOR
IOR
IOR
IOR
IOR
IOR
IOR
IOR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
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