SH7020 Datasheet, PDF (407/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

RDR. If this check passes, the SCI sets RDRF to 1 and stores the received data in the RDR. If
the check does not pass (receive error), the SCI operates as indicated in table 13.8. When the
error flag is set to 1 and the RDRF bit is cleared to 0, the RDRF bit will not be set to 1 during
reception. When restarting the reception, make sure to clear the error flag to 0.
3. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in the
SCR, the SCI requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the
receive-data-full interrupt enable bit (RIE) in the SCR is also set to 1, the SCI requests a
receive-error interrupt (ERI).
Transmitting and Receiving Serial Data Simultaneously (clocked synchronous mode): Figure
13.20 shows a sample flowchart for transmitting and receiving serial data simultaneously. The
procedure for transmitting and receiving serial data simultaneously is listed below.
1. SCI initialization: select the TxD and RxD pin function with the PFC.
2. SCI status check and transmit data write: read the serial status register (SSR), check that the
TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to
0. The TXI interrupt can also be used to determine if the TDRE bit has changed from 0 to 1.
3. Receive error handling: if a receive error occurs, read the ORER bit in SSR to identify the
error. After executing the necessary error handling, clear ORER to 0. Transmitting/receiving
cannot resume if ORER remains set to 1.
4. SCI status check and receive data read: read the serial status register (SSR), check that RDRF
is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0.
The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1.
5. To continue transmitting and receiving serial data: read the RDRF bit and RDR, and clear
RDRF to 0 before the frame MSB (bit 7) of the current frame is received. Also read the TDRE
bit to check whether it is safe to write (1); if so, write data in TDR, then clear TDRE to 0
before the MSB (bit 7) of the current frame is transmitted. When the DMAC is started by a
transmit-data-empty interrupt request (TXI) to write data in TDR, the TDRE bit is checked and
cleared automatically. When the DMAC is started by a receive-data-full interrupt (RXI) to read
RDR, the RDRF bit is cleared automatically.
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