SH7020 Datasheet, PDF (251/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 10.6 Buffer Registers A and B (BRA, BRB)
Channel Abbreviation
3
BRA3, BRB3
4
BRA4, BRB4
Function
When used for buffer operation:
When the corresponding GRA and GRB are output compare
registers, the buffer registers function as output compare buffer
registers that can automatically transfer the BRA and BRB values to
GRA and GRB upon a compare match.
When the corresponding GRA and GRB are input capture registers,
the buffer registers function as input capture buffer registers that can
automatically transfer the values stored until an input capture in the
GRA and GRB to the BRA and BRB.
Bit: 15
14
13
12
11
10
9
8
Bit name:
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Bit name:
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
10.2.9 Timer Control Register (TCR)
The TCR is an 8-bit read/write register that selects the timer counter clock, the edges of the
external clock source, and the counter clear source. Each ITU channel has one TCR. TCR is
initialized H'80 or H'00 by a reset or the standby mode (table 10.7).
Table 10.7 Timer Control Register (TCR)
Abbre-
Channel viation
0
TCR0
1
TCR1
2
TCR2
3
TCR3
4
TCR4
Function
The TCR controls the TCNTs. The TCRs have the same functions on all
channels. When channel 2 is set for phase counting mode, setting the
CKEG1, CKEG2 and TPSC2–TPSC0 bits will have no effect.
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