SH7020 Datasheet, PDF (333/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

11.3.2 Output Timing
If TPC output is enabled, next data register (NDRA/NDRB) contents are transferred to the data
register (PBDR) and output when the selected compare-match occurs. Figure 11.3 shows the
timing of these operations. The example is of ordinary output upon compare match A with groups
2 and 3.
CK
TCNT
N
N+1
GRA
N
Compare
match A
signal
NDRB
n
PBDR
m
n
TP15–TP8
m
n
Figure 11.3 Transfer and Output Timing for NDR Data
11.3.3 Examples of Use of Ordinary TPC Output
Settings for Ordinary TPC Output (figure 11.4):
1. Select GRA as the output compare register (output disable) with the timer I/O control register
(TIOR).
2. Set the TPC output trigger cycle.
3. Select the counter clock with the TPSC2–TPSC0 bits of the timer control register (TCR).
Select the counter clear sources with the CCLR1 and CCLR0 bits.
4. Set the timer interrupt enable register (TIER) to enable IMIA interrupts. Transfers to the NDR
can also be set using the DMAC.
5. Set the initial output value in the I/O port data register to be used by TPC.
6. Set the I/O port control register to be used by TPC as the TP pin function (11).
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