SH7020 Datasheet, PDF (288/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

GRA3
GR
H' 0000
Output pin
Output pin
BR
Duty 0%
Duty 100%
GR
Write on decrement
Write on increment
Figure 10.41 Example of Changing GR Settings with Buffer Operation (2)
The above settings are made by detecting the occurrence of a GRA3 compare match or underflow
of TCNT4 and then writing to BR. They can also be accomplished by starting up the DMAC with
a GRA3 compare match.
10.4.7 Phase Counting Mode
The phase counting mode detects the phase differential of two external clock inputs (TCLKA and
TCLKB) and counts TCNT2 up or down. When set in the phase counting mode, the TCLKA and
TCLKB pins automatically become external clock input pins, regardless of the settings of the
TPSC2–TPSC0 bits of TCR2 or the CKEG1 and CKEG0 bits. TCNT2 also becomes an up/down
counter. Since the TCR2 CCLR1/CCLR0 bits, TIOR2, TIER2, TSR2, GRA2 and GRB2 are all
enabled, input capture and compare match functions and interrupt sources can be used. Phase
counting is available only in channel 2.
Procedure for Selecting the Phase Counting Mode: Figure 10.42 shows the procedure for
selecting the phase counting mode.
1. Set the MDF bit of the timer mode register (TMDR) to 1 to select the phase counting mode.
2. Select the flag set conditions using the FDIR bit of the TMDR.
3. Set the STR2 bit of the timer start register (TSTR) to 1 to start the count.
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