SH7020 Datasheet, PDF (125/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bit 9:
MXC1
0
1
Bit 8:
MXC0
0
1
0
1
Row Address Shift
(MXE = 1)
8 bits (initial value)
9 bits
10 bits
Reserved
Row Address Bits Compared (in burst operation)
(MXE = 0 or 1)
A8–A27 (initial value)
A9–A27
A10–A27
Reserved
Bits 7–0 (reserved): These bits always read as 0. The write value should always be 0.
8.2.6 Refresh Control Register (RCR)
The refresh control register (RCR) is a 16-bit read/write register that controls the start of
refreshing and selects the refresh mode and the number of wait states during refresh. It is
initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or by the standby
mode.
To prevent RCR from being written incorrectly, it must be written by a different method from
most other registers. A word transfer operation is used, H'5A is written in the top byte, and the
actual data is written in the lower byte. For details, see section 8.2.11, Notes on Register Access.
Bit: 15
14
13
12
11
10
9
8
Bit name: —
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: —
—
—
—
—
—
—
—
Bit: 7
6
5
4
3
2
1
0
Bit name: RFSHE RMODE RLW1 RLW0 —
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W
—
—
—
—
• Bit 15–8 (reserved): These bits always read as 0.
• Bit 7 (refresh control (RFSHE)): RFSHE determines whether or not to perform DRAM refresh
operations. When this bit is cleared to 0, no DRAM refresh control is performed and the
refresh timer counter (RTCNT) can be used as an 8-bit interval timer. When set to 1, DRAM
refresh control is performed.
RENESAS 107