SH7020 Datasheet, PDF (309/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

10.6.10 Contention Between BR Write and Input Capture
When a buffer register (BR) is being used as an input capture register and an input capture signal
is generated in the T3 state of the write cycle, the buffer operation takes priority over the BR write.
The timing is shown in figure 10.66.
BR write cycle
T1
T2
T3
CK
Address
Internal
write signal
Input capture
signal
GR
BR
BR address
N
X
TCNT value
M
N
Figure 10.66 Contention between BR Write and Input Capture
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