SH7020 Datasheet, PDF (310/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

10.6.11 Note on Writing in the Synchronizing Mode
After the synchronizing mode is selected, if the TCNT is written by byte access, all 16 bits of all
synchronized counters assume the same value as the counter that was addressed.
Example: Figures 10.67 and 10.68 show byte write and word write when channels 2 and 3 are
synchronized
TCNT2
W
TCNT3
Y
Upper
byte
X
Z
Lower
byte
Write A to upper
byte of channel 2 _TCNT2
A
Write A to lower
byte of channel 3
TCNT3
TCNT2
A
Upper
byte
Y
TCNT3
Y
Upper
byte
X
X
Lower
byte
A
A
Lower
byte
Figure 10.67 Byte Write to Channel 2 or Byte Write to Channel 3
TCNT2
W
TCNT3
Y
Upper
byte
X
Z
Lower
byte
TCNT2
Word write of AB TCNT3
for channel 2 or 3
A
A
Upper
byte
B
B
Lower
byte
Figure 10.68 Word Write to Channel 2 or Word Write to Channel 3
10.6.12 Note on Setting Reset-synchronized PWM Mode/Complementary PWM Mode
When the CMD1 and CMD0 bits of TFCR are set, note the following.
1. Writes to CMD1 and CMD0 should be done while TCNT3 and TCNT4 are halted.
2. Changes of setting from the reset-synchronized PWM mode to the complementary PWM mode
and vice versa are inhibited. Set the reset-synchronized PWM mode or complementary PWM
mode after first setting normal operation (clear CMD1 bit to 0).
294 RENESAS