SH7020 Datasheet, PDF (405/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

cannot resume if ORER remains set to 1.
3. SCI status check and receive data read: read the serial status register (SSR), check that RDRF
is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0.
The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1.
4. To continue receiving serial data: read RDR, and clear RDRF to 0 before the frame MSB (bit
7) of the current frame is received. If the DMAC is started by a receive-data-full interrupt
(RXI) to read RDR, the RDRF bit is cleared automatically so this step is unnecessary.
Initialization
(1)
Start receiving
Read the ORER bit of the SSR
ORER = 1?
No
Yes
(2)
Error handling
Read RDRF bit of the SSR (3)
No
RDRF = 1?
Yes
Read the RDR's receive data ₍₄₎
and clear the SSR's RDRF bit to 0
No
Total count received?
Yes
Clear the RE bit of the SCR to 0
Reception ends
Figure 13.18 Sample Flowchart for Serial Receiving
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