SH7020 Datasheet, PDF (114/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 8.2 Register Configuration
Name
Abbr. R/W Initial Value Address*¹ Bus width
Bus control register
BCR
R/W H'0000
H'5FFFFA0 8,16,32
Wait state control register 1
WCR1 R/W H'FFFF
H'5FFFFA2 8,16,32
Wait state control register 2
WCR2 R/W H'FFFF
H'5FFFFA4 8,16,32
Wait state control register 3
WCR3 R/W H'F800
H'5FFFFA6 8,16,32
DRAM area control register
DCR
R/W H'0000
H'5FFFFA8 8,16,32
Parity control register
PCR
R/W H'0000
H'5FFFFAA 8,16,32
Refresh control register
RCR
R/W H'0000
H'5FFFFAC 8,16,32*²
Refresh timer control/status register RTCSR R/W H'0000
H'5FFFFAE 8,16,32*²
Refresh timer counter
RTCNT R/W H'0000
H'5FFFFB0 8,16,32*²
Refresh time constant register
RTCOR R/W H'00FF
H'5FFFFB2 8,16,32*²
Notes: 1. Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Description of Areas.
2. Write only with word transfer instructions. See section 8.2.11, Register Access, for
details on writing.
8.1.5 Overview of Areas
The SH microprocessors have 32-bit address spaces on the architecture, but the top 4 bits are
ignored. Table 8.3 outlines the division of space. As shown, the space is divided into areas 0–7 by
the value of the top addresses.
Each area is allocated a specific type of space. When the area is accessed, a strobe signal that
matches the type of area space is generated. This allocates peripheral LSIs and memory devices
according to the type of the area spaces and allows them to be directly linked to this LSI. Some
areas are of a fixed type based on their address while others can be selected in registers.
Area 0 can be used as an on-chip ROM space or external memory space. Area 1 can be used as
DRAM space or external memory space. DRAM space enables direct connection to DRAM and
outputs RAS, CAS and multiplexed addresses. Areas 2–4 can only be used as external memory
space. Area 5 can be used as on-chip peripheral module space or external memory space. Area 6
can be used as address/data multiplexed I/O space or external memory space. For address/data
multiplexed I/O space, an address and data are multiplexed and input/output from AD15–AD0
pins. Area 7 can be used as on-chip RAM space or external memory space.
The bus width of the data bus is basically switched between 8 bit and 16 bit by the value of
address bit A27. For the following areas, however, the bus width is determined by conditions other
than the A27 bit value.
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