SH7020 Datasheet, PDF (224/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

9.4.2 Example of DMA Transfer between On-Chip SCI and External Memory
In this example, receive data of on-chip serial communications interface (SCI) channel 0 is
transferred to external memory using DMAC channel 3. Table 9.8 shows the transfer conditions
and register settings.
Table 9.8 Transfer Conditions and Register Settings for Transfer between On-Chip SCI
and External Memory
Transfer Conditions
Transfer source: RDR0 of on-chip SCI0
Transfer destination: external memory
Number of transfers: 64
Transfer destination address: incremented
Transfer source address: fixed
Transfer request source (transfer request signal): SCI0 (RXI0)
Bus mode: cycle steal
Transfer unit: byte
DEI interrupt request generated at end of transfer (channel 3
enabled for transfer
Channel priority order: fixed (0 > 3 > 2 > 1) (all channels
transfer enabled)
Register
SAR3
DAR3
TCR3
CHCR3
DMAOR
Setting
H'FFFFEC5
Destination address
H'0040
H'4405
H'0001
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