SH7020 Datasheet, PDF (51/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Instruction codes, operation, and execution states are listed in the following format in order by
classification.
Table 2.11 Instruction Code Format
Item
Format
Explanation
Instruction
mnemonic
OP.Sz
SRC,DEST
OP: Operation code
Sz: Size
SRC: Source
DEST: Destination
Rm: Source register
Rn: Destination register
imm: Immediate data
disp: Displacement*
Instruction
code
MSB ↔ LSB
mmmm: Source register
nnnn: Destination register
0000: R0
0001: R1
...........
1111: R15
iiii: Immediate data
dddd: Displacement
Operation
summary
→, ←
(xx)
M/Q/T
&
|
^
~
<<n, >>n
Direction of transfer
Memory operand
Flag bits in the SR
Logical AND of each bit
Logical OR of each bit
Exclusive OR of each bit
Logical NOT of each bit
n-bit shift
Execution
cycle
Value when no wait states are inserted
Instruction execution cycles: The execution cycles shown in
the table are minimums. The actual number of cycles may
be increased:
1. When contention occurs between instruction fetches
and data access, or
2. When the destination register of the load instruction
(memory → register) and the register used by the next
instruction are the same.
T bit
Value of T bit after instruction is executed
—
No change
Note: Scaling (×1, ×2, ×4) is performed according to the instruction operand size. See
"SH-1/SH-2 Programming Manual" for details.
30 RENESAS