SH7020 Datasheet, PDF (260/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Internal data bus
CPU
Bus
interface
Module
data bus
TCR
Figure 10.12 TCR Access (CPU–TCR)
Internal data bus
CPU
Bus
interface
Module
data bus
TCR
Figure 10.13 TCR Access (TCR–CPU )
10.4 Description of Operation
10.4.1 Overview
The operation modes are described below.
Ordinary Operation: Each channel has a timer counter (TCNT) and general register (GR). The
TCNT is an upcounter and can also operate as a free-running counter, periodic counter or external
event counter. General registers A and B (GRA and GRB) can be used as output compare registers
or input capture registers.
Synchronized Operation: The TCNT of a channel set for synchronized operation does a
synchronized preset. When any TCNT of a channel operating in the synchronized mode is
rewritten, the TCNTs of other channels are simultaneously rewritten as well. The CCLR1 and
CCLR0 bits of the timer control register of multiple channels set for synchronous operation can be
set to clear the TCNTs simultaneously.
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