SH7020 Datasheet, PDF (68/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Reset
Address
error
Exception
source
Interrupt
• Power-on reset
• Manual reset
• CPU address error
• DMA address error
Priority
High
• NMI
• User break
• IRQ
• On-chip module
• IRQ0–IRQ7
• Direct memory access
controller
• 16-bit integrated-timer
pulse unit
• Serial communications
interface
• Parity control unit
(part of the bus con-
troller)
• Watchdog timer
• DRAM refresh control
unit (part of the bus
controller)
• Trap instruction
• TRAPA instruction
Notes: 1.
2.
Instruction
• General illegal
instruction
• Illegal slot
instruction
• Undefined code
• Undefined instruction
or instruction that
rewrites the PC*¹
placed directly after ^Low
a delayed branch
instruction*²
The instructions that rewrite the PC are JMP, JSR, BRA, BSR, RTS, RTE, BT, BF,
and TRAPA.
The delayed branch instructions are JMP, JSR. BRA. BSR, RTS, and RTE.
Figure 4.1 Exception Source Types and Priority
48 RENESAS