SH7020 Datasheet, PDF (392/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Transmitting
processor
Serial communication line
Receiving
processor A
(ID = 01)
Receiving
processor B
(ID = 02)
Receiving
processor C
(ID = 03)
Receiving
processor D
(ID = 04)
Serial
data
H'01
(MPB = 1)
ID-sending cycle:
receiving processor address
MPB: multiprocessor bit
H'AA
(MPB = 0)
Data-sending cycle:
data sent to receiving
processor specified by ID
Figure 13.9 Example of Communication among Processors Using Multiprocessor Format
(sending data H'AA to receiving processor A)
Communication Formats: Four formats are available. Parity-bit settings are ignored when the
multiprocessor format is selected. For details see table 13.8.
Clock: See the description in the asynchronous mode section.
Transmitting Multiprocessor Serial Data: Figure 13.10 shows a sample flowchart for
transmitting multiprocessor serial data. The procedure for transmitting multiprocessor serial data is
listed below.
1. SCI initialization: select the TxD pin function with the PFC.
2. SCI status check and transmit data write: read the serial status register (SSR), check that the
TDRE bit is 1, then write transmit data in the transmit data register (TDR). Also set MPBT
(multiprocessor bit transfer) to 0 or 1 in SSR. Finally, clear TDRE to 0.
3. To continue transmitting serial data: read the TDRE bit to check whether it is safe to write (1);
if so, write data in TDR, then clear TDRE to 0. When the DMAC is started by a transmit-data-
empty interrupt request (TXI) to write data in TDR, the TDRE bit is checked and cleared
automatically.
4. To output a break signal at the end of serial transmission: set the DR bit to 0 (I/O data port
register), then clear TE to 0 in SCR and set the TxD pin function as output port with the PFC.
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