SH7020 Datasheet, PDF (63/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

From any state when
RES = 0 and NMI = 1
From any state when
RES = 0 and NMI = 0
Power-on reset state
RES = 0, NMI = 0
RES = 0, NMI = 1
Manual reset state
When an interrupt source
or DMA address error occurs
RES = 1,
NMI = 1
RES = 1,
NMI = 0
Exception processing state
Reset states
Bus request
cleared
Bus request
generated
Bus release state
Exception
processing
source occurs
Bus request
generated
Bus request
cleared
NMI interrupt
source occurs
Exception
processing
ends
Bus request
generated
Bus request
cleared
Program execution state
SBY bit cleared for
SLEEP instruction
SBY bit set
for SLEEP
instruction
Sleep mode
Standby mode
Power-down state
Figure 2.6 Transitions Between Processing States
Reset State: In the reset state the CPU is reset. This occurs when the RES pin level goes low.
When the NMI pin is high, the result is a power-on reset; when it is low, a manual reset will
occur.When turning on the power, make sure to carry out a power-on reset.
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