SH7020 Datasheet, PDF (366/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

13.2.7 Serial Status Register
The serial status register (SSR) is an 8-bit register containing multiprocessor bit values, and status
flags that indicate SCI operating status.
The CPU can always read and write the SSR, but cannot write 1 in the status flags (TDRE, RDRF,
ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read (after
being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written. The SSR is
initialized to H'84 by a reset or in standby mode.
Bit: 7
Bit name: TDRE
Initial value: 1
R/W: R/(W)*
Note: Write 0 to clear flag.
6
RDRF
0
R/(W)*
5
ORER
0
R/(W)*
4
FER
0
R/(W)*
3
PER
0
R/(W)*
2
TEND
1
R
1
MPB
0
R
0
MPBT
0
R/W
• Bit 7 (transmit data register empty (TDRE)): TDRE indicates that the SCI has loaded transmit
data from the TDR into the TSR and serial transmit new data can be written in the TDR.
Bit 7: TDRE
0
1
Description
TDR contains valid transmit data
TDRE is cleared to 0 when:
• Software reads TDRE after it has been set to 1, then writes 0 in TDRE
• The DMAC writes data in TDR
TDR does not contain valid transmit data (initial value)
TDRE is set to 1 when:
• The chip is reset or enters standby mode
• The TE bit in the serial control register (SCR) is cleared to 0
• TDR contents are loaded into TSR, so new data can be written in TDR
RENESAS 351