SH7020 Datasheet, PDF (47/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 2.9 Instruction Formats (cont)
Instruction Formats
m format
Source
Operand
mmmm: Direct
register
Destination
Operand
Control register or
system register
Instruction
Example
LDC Rm,SR
15
0
xxxx mmmm xxxx xxxx
nm format
15
0
xxxx nnnn mmmm xxxx
mmmm: Indirect
post-increment
register
mmmm: Direct
register
mmmm: Direct
register
mmmm: Direct
register
Control register or
system register
—
nnnn: Direct
register
nnnn: Direct
register
LDC.L
@Rm+,SR
JMP @Rm
ADD Rm,Rn
MOV.L Rm,@Rn
md format
15
xxxx
0
xxxx mmmm dddd
nd4 format
15
xxxx xxxx
nnnn
0
dddd
mmmm: Indirect
post-increment
register (multiply/
accumulate)
MACH, MACL
MAC.W
@Rm+,@Rn+
nnnn: Indirect
post-increment
register (multiply/
accumulate)*
mmmm: Indirect
post-increment
register
nnnn: Direct
register
MOV.L
@Rm+,Rn
mmmm: Direct
register
nnnn: Indirect pre- MOV.L Rm,@-
decrement register Rn
mmmm: Direct
register
nnnn: Indirect
indexed register
MOV.L
Rm,@(R0,Rn)
mmmmdddd:
indirect register
with
displacement
R0 (Direct register) MOV.B
@(disp,Rm),R0
R0 (Direct
register)
nnnndddd: Indirect MOV.B
register with
R0,@(disp,Rn)
displacement
Note: In MAC instructions, nnnn is the source register.
26 RENESAS