SH7020 Datasheet, PDF (41/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

cycles.
T bit: T bit (in the status register) is set according to the result of a comparison, and in turn is the
condition (True/False) that determines if the program will branch. The T bit in the status register is
only changed by selected instructions, thus improving the processing speed.
Table 2.4 T bit
CPU of SH7000 Series
CMP/GE R1, R0
BT
TRGET0
BF
TRGET1
ADD #–1, R0
TST R0, R0
BT
TRGET
Description
Conventional CPU
T bit is set when R0 ≥ R1. The program
branches to TRGET0 when R0 ≥ R1
and to TRGET1 when R0<R1.
CMP.W R1, R0
BGE TRGET0
BLT TRGET1
T bit is not changed by ADD. T bit is set SUB.W #1, R0
when R0=0. The program branches if BEQ TRGET
R0=0.
Immediate Data: Byte (8-bit) immediate data is located in the instruction code. Word or long
word immediate data is not located in instruction codes but is stored in a memory table. The
memory table is accessed by a immediate data transfer instruction (MOV) using the PC relative
addressing mode with displacement.
Table 2.5 Immediate Data Accessing
Classification
CPU of SH7000 Series
Conventional CPU
8-bit immediate
MOV #H'12, R0
MOV.B #H'12, R0
16-bit immediate
MOV.W @(disp,PC), R0
.........
.DATA.W
H'1234
MOV.W #H'1234, R0
32-bit immediate
MOV.L @(disp,PC), R0
.........
.DATA.L
H'12345678
MOV.L #H'12345678, R0
Note: The address of the immediate data is accessed by @(disp, PC).
Absolute Address: When data is accessed by absolute address, the value already in the absolute
address is placed in the memory table. By loading the immediate data when the instruction is
executed, that value is transferred to the register and the data is accessed in the indirect register
addressing mode.
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