SH7020 Datasheet, PDF (168/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

enter the self-refresh mode when the CAS and RAS signals are output as shown in figure 8.31. See
section 20.3.3, Bus Timing, for details. The DRAM self-refresh mode is cleared when the
RMODE bit in the RCR is cleared to 0 (figure 8.31). The RFSHE bit should be left at 1 when this
is done. Some DRAM vendors recommend that after exiting the self-refresh mode, all row
addresses should be refreshed again. This can be done using the BCR’s CBR refresh function to
set all row addresses for refresh in software.
To access a DRAM area in the self-refresh mode, clear the RMODE bit to 0 and exit the self-
refresh mode.
The LSI can be kept in the self-refresh state and shifted to standby mode by setting it to self-
refresh mode, setting the standby bit (SBY) of the standby control register (SBYCR) to 1, and then
executing a SLEEP instruction.
CK
RAS
CAS
T_Rp
T_Rr
T_Rc
T_Rcc
Figure 8.31 Output Timing of Self-Refresh Signal
Refresh Requests and Bus Cycle Requests: When a CAS-before-RAS refresh or self-refresh is
requested during bus cycle execution, parallel execution is sometimes possible. Table 8.10
describes operation when the refresh and bus cycle are in contention.
150 RENESAS