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SH7020 Datasheet, PDF (394/509 Pages) Renesas Technology Corp – SuperH™ RISC engine
1. The SCI monitors the TDRE bit in the SSR. When TDRE is cleared to 0 the SCI recognizes
that the transmit data register (TDR) contains new data, and loads this data from the TDR into
the transmit shift register (TSR).
2. After loading the data from the TDR into the TSR, the SCI sets the TDRE bit to 1 and starts
transmitting. If the transmit-data-empty interrupt enable bit (TIE) in the SCR is set to 1, the
SCI requests a transmit-data-empty interrupt (TXI) at this time.
Serial transmit data is transmitted in the following order from the TxD pin (figure 13.11):
1. Start bit: one 0 bit is output.
2. Transmit data: seven or eight bits are output, LSB first.
3. Multiprocessor bit: one multiprocessor bit (MPBT value) is output.
4. Stop bit: one or two 1 bits (stop bits) are output.
5. Mark state: output of 1 bits continues until the start bit of the next transmit data.
6. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads data
from the TDR into the TSR, outputs the stop bit, then begins serial transmission of the next
frame. If TDRE is 1, the SCI sets the TEND bit in the SSR to 1, outputs the stop bit, then
continues output of 1 bits in the mark state. If the transmit-end interrupt enable bit (TEIE) in
the SCR is set to 1, a transmit-end interrupt (TEI) is requested at this time.
1
Serial
data
Start
bit
0 D0
Multi-
processor Stop Start
Data bit bit bit
D1
D7 0/1 1 0 D0
Multi-
processorStop
Data bit bit
1
D1
D7
0/1
1 Idle (mark
state)
TDRE
TEND
TXI TXI interrupt
request handler writes
data in TDR and
clears TDRE to 0
1 frame
TXI
request
TEI
request
Figure 13.11 Example of SCI Multiprocessor Transmit Operation (8-bit data with
multiprocessor bit and one stop bit)
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