SH7020 Datasheet, PDF (78/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

4.7 Stack Status after Exception Processing
Table 4.10 shows the stack after exception processing.
Table 4.10 Stack after Exception Processing
Type
Stack Status
Address
error
Address of
SP instruction Upper 16 bits
after instruc-
tion that has
finished
executing
Lower 16 bits
SR Upper 16 bits
Lower 16 bits
Type
Stack Status
Interrupt
Address of
SP instruction Upper 16 bits
after instruc-
tion that
has finished
executing
Lower 16 bits
SR Upper 16 bits
Lower 16 bits
Trap
instruc-
tion
Address of
SP instruction Upper 16 bits
after TRAPA
instruction
Lower 16 bits
SR Upper 16 bits
Lower 16 bits
Illegal
slot
instruc-
tion
Branch
SP destination
address of
delayed
branch
instuction
SR
Upper 16 bits
Lower 16 bits
Upper 16 bits
Lower 16 bits
General
illegal
instruc-
SP
Start add-
ress of
Upper 16 bits
tion
illegal
instruction
Lower 16 bits
SR Upper 16 bits
Lower 16 bits
Note: Stack status is based on a bus width of 16 bits.
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