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SH7020 Datasheet, PDF (494/509 Pages) Renesas Technology Corp – SuperH™ RISC engine
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CK
A21–A0
RAS
CAS
RD(Read)
Tp
Tr
Tc1
Tc2
tAD
tAD
Row
tRASD1
Column
Tc1
Tc2
Column
tRDD
tCASD2
tCASD3
tRSD
tRASD2
tCASD3
WRH, WRL,
(Read)
AD15–AD0
DPH, DPL
(Read)
DACK0
DACK1
(Read)
tRAC2*3
tACC2*2 tCAC2*tR1DS tRDH*4
tDACD1
tDACD2 tDACD1
tRDH*5
tDACD2
RD(Write)
tWSD1
tWSD2
tWSD1
tWSD2
WRH, WRL,
(Write)
AD15–AD0
(Write)
DPH, DPL
(Write)
DACK0
DACK1
(Write)
tWDD1
tWPDD1
tWDH tWDD1
tWPDH tWPDD1
tWDH
tWPDH
tDACD3
tDACD3
tDACD3 tDACD3
Notes: 1.
2.
3.
4.
5.
For tCAC2, use tcyc × (n + 1) – 35 instead of tcyc × (n + 1) – tCASD2 – tRDS.
For tACC2, use tcyc × (n + 2) – 44 instead of tcyc × (n + 2) – tAD – tRDS.
For tRAC2, use tcyc × (n + 2.5) – 35 instead of tcyc × (n + 2.5) – tRASD1 – tRDS.
tRDH is measured from A21–A0 or CAS, whichever is negated first.
tRDH is measured from A21–A0, RAS, or CAS whichever is negated first.
Figure 19.27 DRAM Bus Cycle: (Long Pitch, High-Speed Page Mode)
RENESAS 484
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