SH7020 Datasheet, PDF (246/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

10.2.4 Timer Function Control Register (TFCR)
The timer function control register (TFCR) is an 8-bit read/write register that selects
complementary PWM/reset-synchronized PWM for channels 3 and 4 and sets the buffer operation.
TFCR is initialized on a reset or standby mode to H'C0 or H'40.
Bit: 7
Bit name: —
Initial value:
*
R/W: —
Note: Undefined
6
5
4
3
2
1
0
— CMD1 CMD0 BFB4 BFA4 BFB3 BFA3
1
0
0
0
0
0
0
—
R/W R/W R/W R/W R/W R/W
• Bits 7 and 6 (reserved): Bit 7 is read as undefined. Bit 6 is always read as 1. The write value to
bit 7 should be 0 or 1. The write value to bit 6 should always be 1.
• Bits 5 and 4 (combination mode 1 and 0 (CMD1 and CMD0)): CMD1 and CMD0 select the
complementary PWM mode or reset-synchronized mode for channels 3 and 4. Set the
complementary PWM/reset-synchronized PWM mode while the timer counter (TCNT) being
used is off. When these bits are used to set the complementary PWM/reset-synchronized PWM
mode, they take priority over the PWM4 and PWM3 bits of the TMDR. While the
complementary PWM/reset-synchronized PWM mode settings and the SYNC4 and SYNC3 bit
settings of the timer synchro register (TSNC) are valid simultaneously, when the
complementary PWM mode is set, channels 3 and 4 should not be set to operate
simultaneously (SYNC 4 and SYNC 3 bits of TSNC should not both be set to 1).
Bit 5: CMD1
0
1
Bit 4: CMD0
0
1
0
1
Description
Channels 3 and 4 operate normally (initial value)
Channels 3 and 4 operate normally
Channels 3 and 4 operate together in complementary PWM
mode
Channels 3 and 4 operate together in reset-synchronized
PWM mode
• Bit 3 (buffer mode B4 (BFB4)): BFB4 selects the buffer mode for GRB4 and BRB4 in channel
4.
Bit 3: BFB4
0
1
Description
GRB4 operates normally in channel 4 (initial value)
GRB4 and BRB4 operate in buffer mode in channel 4
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