SH7020 Datasheet, PDF (268/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

• Compare match output timing
The compare match signal is generated in the last state in which the TCNT and the general
register match (when the TCNT changes from the matching value to the next value). When a
compare match signal is generated, the output value set in TIOR is output to the output
compare pin (TIOCA, TIOCB). Accordingly, when the TCNT matches a general register, the
compare match signal is not generated until the next counter clock pulse. Figure 10.22 shows
the output timing of the compare match signal.
CK
TCNT input
clock
TCNT
N
N–1
GR
N
Compare
match signal
TIOCA
TIOCB
Figure 10.22 Compare Match Signal Output Timing
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