SH7020 Datasheet, PDF (429/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 15.1 Port A Register
Name
Abbreviation R/W Initial Value Address
Access Size
Port A data register PADR
R/W H'0000
H'5FFFFC0 8, 16, 32
15.2.2 Port A Data Register (PADR)
PADR is a 16-bit read/write register that stores data for port A. The bits PA15DR–PA0DR
correspond to the PA15/IRQ3/DREQ1–PA0/CS4/TIOCA0 pins. When the pins are used as
ordinary outputs, they will output whatever value is written in the PADR; when PADR is read, the
register value will be output regardless of the pin status. When the pins are used as ordinary
inputs, the pin status rather than the register value is read directly when PADR is read. When a
value is written to PADR, that value can be written into PADR, but it will not affect the pin status.
Table 15.2 shows the read/write operations of the port A data register.
PADR is initialized by a power-on reset. However, PADR is not initialized for manual reset,
standby mode, or sleep mode.
Bit:
15
14
13
12
11
10
9
8
Bit name: PA15DR PA14DR PA13DR PA12DR PA11DR PA10DR PA9DR PA8DR
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
Bit name:
Initial value:
R/W:
7
6
5
4
3
2
1
0
PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W
Table 15.2 Read/Write Operation of the Port A Data Register (PADR)
PAIOR
0
Pin Status
Input
Read
Pin status
Other function Pin status
1
Output
PADR value
Other function PADR value
Write
Can write to PADR, but it has no effect on pin
status.
Can write to PADR, but it has no effect on pin
status.
Value written is output by pin
Can write to PADR, but it has no effect on pin
status.
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