SH7020 Datasheet, PDF (273/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Synchronized Operation: Figure 10.27 shows an example of synchronized operation. Channels
0, 1, and 2 are set to synchronized operation and PWM output. Channel 0 is set for a counter clear
upon compare match with GRB0. Channels 1 and 2 are set for counter clears by synchronizing
clears. Accordingly, their timers are sync preset, then sync cleared by a GRB0 compare match,
and then a three-phase PWM waveform is output from the TIOCA0, TIOCA1 and TIOCA2 pins.
See section 10.4.4, PWM Mode, for details on the PWM mode.
TCNT0–TCNT2 values
GRB0
GRB1
GRA0
GRB2
GRA1
GRA2
Synchronized clear on GRB0 compare match
TIOCA0
Time
TIOCA1
TIOCA2
Figure 10.27 Synchronized Operation Example
RENESAS 257