SH7020 Datasheet, PDF (368/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

• Bit 4 (framing error (FER)): FER indicates that data reception ended abnormally due to a
framing error in the asynchronous mode.
Bit 4: FER
0
1
Description
Receiving is in progress or has ended normally. Clearing the RE bit to 0 in the
serial control register does not affect the FER bit, which retains its previous
value (initial value).
FER is cleared to 0 when:
• The chip is reset or enters standby mode
• Software reads FER after it has been set to 1, then writes 0 in FER
A receive framing error occurred. When the stop bit length is two bits, only the
first bit is checked. The second stop bit is not checked. When a framing error
occurs, the SCI transfers the receive data into the RDR but does not set RDRF.
Serial receiving cannot continue while FER is set to 1. In the clocked
synchronous mode, serial transmitting is also disabled.
FER is set to 1 if the stop bit at the end of receive data is checked and found to
be 0.
• Bit 3 (parity error (PER)): PER indicates that data reception (with parity) ended abnormally
due to a parity error in the asynchronous mode.
Bit 3: PER
0
1
Description
Receiving is in progress or has ended normally. Clearing the RE bit to 0 in the
serial control register does not affect the PER bit, which retains its previous
value (initial value).
PER is cleared to 0 when:
• The chip is reset or enters standby mode
• Software reads PER after it has been set to 1, then writes 0 in PER
A receive parity error occurred. When a parity error occurs, the SCI transfers the
receive data into the RDR but does not set RDRF. Serial receiving cannot
continue while PER is set to 1. In the clocked synchronous mode, serial
transmitting is also disabled.
PER is set to 1 if the number of 1s in receive data, including the parity bit, does
not match the even or odd parity setting of the parity mode bit (O/E) in the serial
mode register (SMR).
RENESAS 353