SH7020 Datasheet, PDF (43/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

2.3.2 Addressing Modes
Addressing modes and effective address calculation are described in table 2.8.
Table 2.8 Addressing Modes and Effective Addresses
Addressing Mnemonic
Mode
Expression Effective Addresses Calculation
Equation
Direct
Rn
register
addressing
The effective address is register Rn. (The operand is —
the contents of register Rn.)
Indirect
register
addressing
@Rn
The effective address is the content of register Rn. Rn
Rn
Rn
Post-incre-
ment
indirect
register
addressing
@Rn +
The effective address is the content of register Rn. A
constant is added to the content of Rn after the
instruction is executed. 1 is added for a byte
operation, 2 for a word operation, and 4 for a long
word operation.
Rn
Rn
Rn
(After the
instruction is
executed)
Byte: Rn + 1
→ Rn
Rn + 1/2/4 ₊
Word: Rn + 2
→ Rn
1/2/4
Long word:
Rn + 4 → Rn
Pre-decre-
ment
indirect
register
addressing
@–Rn
The effective address is the value obtained by
subtracting a constant from Rn. 1 is subtracted for a
byte operation, 2 for a word operation, and 4 for a
long word operation.
Rn
Rn – 1/2/4 _–
Rn – 1/2/4
1/2/4
Byte: Rn – 1
→ Rn
Word: Rn – 2
→ Rn
Long word:
Rn – 4 → Rn
(Instruction
executed with
Rn after
calculation)
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