SH7020 Datasheet, PDF (113/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

8.1.3 Pin Configuration
Table 8.1 shows the BSC pin configuration.
Table 8.1 Pin Configuration
Name
Abbreviation I/O Function
Chip select 7–0
CS7–CS0
O Chip select signal that indicates the area being
accessed
Read
RD
O Strobe signal that indicates the read cycle
High write
WRH
O Strobe signal that indicates write cycle to upper 8 bits
Low write
Write
High byte strobe
Low byte strobe
WRL
WR*¹
HBS*²
LBS*³
O Strobe signal that indicates write cycle to lower 8 bits
O Strobe signal that indicates write cycle
O Strobe signal that indicates access to upper 8 bits
O Strobe signal that indicates access to lower 8 bits
Row address strobe RAS
O DRAM row address strobe signal
High column
address strobe
CASH
O Column address strobe signal for accessing the
upper 8 bits of the DRAM
Low column address CASL
strobe
O Column address strobe signal for accessing the lower
8 bits of the DRAM
Address hold
AH
O Signal for holding the address for address/data
multiplexing
Wait
WAIT
I Wait state request signal
Address bus
A21–A0
O Address output
Data bus
AD15–AD0
I/O Data I/O. During address/data multiplexing, address
output and data input/output.
Data bus parity high DPH
I/O Parity data I/O for upper byte
Data bus parity low DPL
I/O Parity data I/O for lower byte
Notes: 1. Doubles with the WRL pin. (Selected by the BAS bit of the BCR. See section 8.2.1, Bus
Control Register, for details.
2. Doubles with the A0 pin. (Selected by the BAS bit of the BCR. See section 8.2.1, Bus
Control Register, for details.
3. Doubles with the WRH pin. (Selected by the BAS bit of the BCR. See section 8.2.1, Bus
Control Register, for details.
8.1.4 Register Configuration
The BSC has ten registers (listed in table 8.2) which control space division, wait states, DRAM
interface, and parity check.
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