SH7020 Datasheet, PDF (329/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

11.2.7 TPC Output Control Register (TPCR)
TPCR is an eight-bit read/write register that selects output trigger signals for TPC outputs. When
reset, TPCR is initialized to H'FF. It is not initialized by standby mode.
Bit: 7
6
5
4
3
2
1
0
Bit name: G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
• Bits 7 and 6 (group 3 compare-match select 1 and 0 (G3CMS1 and G3CMS0)): G3CMS1 and
G3CMS0 select the compare match that triggers TPC output group 3 (TP15–TP12).
Bit 7: G3CMS1 Bit 6: G3CMS0 Description
0
0
TPC output group 3 (TP15–TP12) output is triggered by
compare-match in ITU channel 0
1
TPC output group 3 (TP15–TP12) output is triggered by
compare-match in ITU channel 1
1
0
TPC output group 3 (TP15–TP12) output is triggered by
compare-match in ITU channel 2
1
TPC output group 3 (TP15–TP12) output is triggered by
compare-match in ITU channel 3 (initial value)
• Bits 5 and 4 (group 2 compare-match select 1 and 0 (G2CMS1 and G2CMS0)): G2CMS1 and
G2CMS0 select the ITU channel that triggers TPC output group 2 (TP11–TP8).
Bit 5: G2CMS1 Bit 4: G2CMS0 Description
0
0
TPC output group 2 (TP11–TP18) output is triggered by
compare-match in ITU channel 0
1
TPC output group 2 (TP11–TP18) output is triggered by
compare-match in ITU channel 1
1
0
TPC output group 2 (TP11–TP18) output is triggered by
compare-match in ITU channel 2
1
TPC output group 2 (TP11–TP18) output is triggered by
compare-match in ITU channel 3 (initial value)
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