SH7020 Datasheet, PDF (249/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 10.4 Timer Counters (TCNT)
Channel Abbreviation
0
TCNT0
1
TCNT1
2
TCNT2
3
TCNT3
4
TCNT4
Function
Increment counter
Phase counting mode: Increment/decrement
All others: Increment
Complementary PWM mode: Increment/decrement
All others: Increment
Bit: 15
14
13
12
11
10
9
8
Bit name:
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Bit name:
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
10.2.7 General Registers A and B (GRA and GRB)
Each of the five ITU channels has two 16-bit general registers (GR) for a total of ten registers
(table 10.5).
Each GR is a 16-bit read/write register that can function as either an output compare register or an
input capture register. The function is selected by settings in the timer I/O control register (TIOR).
When a general register (GRA/GRB) is used as an output compare register, its value is constantly
compared with the timer counter (TCNT) value. When the two values match (compare match), the
IMFA/IMFB bit is set to 1 in the timer status register (TSR). If compare match output is selected
in the TIOR, a specified value is output at the output compare pin.
When a general register is used as an input capture register, an external input capture signal is
detected and the TCNT value is stored. The IMFA/IMFB bit of the corresponding TSR is set to 1
at the same time. The valid edge or edges of the input capture signal are selected in the TIOR. The
TIOR setting is ignored when set for the PWM mode, complementary PWM mode or reset-
synchronized PWM mode.
RENESAS 233