SH7020 Datasheet, PDF (326/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

11.2.4 Next Data Register B (NDRB)
NDRB is an eight-bit read/write register that stores the next output data for TPC output groups 3
and 2 (TP15–TP8). When used for TPC output, the contents of the NDRB are transferred to the
corresponding PBDR bits when the ITU compare match specified in the TPC output control
register TPCR occurs.
The address of the NDRB differs depending on whether TPCR settings select the same trigger or
different triggers for TPC output groups 3 and 2. When reset, NDRB is initialized to H'00. It is not
initialized by standby mode.
Same Trigger for TPC Output Groups 3 and 2: If TPC output groups 3 and 2 are triggered by the
same compare match, the address of the NDRB is H'FFFFF4. The 4 upper bits becomes group 3
and the 4 lower bits become group 2. Address H'5FFFFF6 becomes completely reserved bits.
These bits always read as 1, and the write value should always be 1.
Address H'5FFFFF4:
• Bits 7–4 (next data 15–12 (NDR15–NDR12)): NDR15–NDR12 store next output data for TPC
output group 3.
• Bits 3–0 (next data 11–8 (NDR11–NDR8)): NDR11–NDR8 store next output data for TPC
output group 2.
Bit:
Bit name:
Initial value:
R/W:
7
NDR15
0
R/W
6
NDR14
0
R/W
5
NDR13
0
R/W
4
NDR12
0
R/W
3
NDR11
0
R/W
2
NDR10
0
R/W
1
NDR9
0
R/W
0
NDR8
0
R/W
Address H'5FFFFF6:
• Bits 7–0 (reserved): These bits always read as 1. The write value should always be 1.
Bit: 7
6
5
4
3
2
1
0
Bit name: —
—
—
—
—
—
—
—
Initial value: 1
1
1
1
1
1
1
1
R/W: —
—
—
—
—
—
—
—
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