SH7020 Datasheet, PDF (253/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bit 2: Bit 1: Bit 0:
TPSC2 TPSC1 TPSC0 Counter Clock (and cycle when φ = 10 MHz)
0
0
0
Internal clock φ (initial value)
1
Internal clock φ/2
1
0
Internal clock φ/4
1
Internal clock φ/8
1
0
0
External clock A (TCLKA)
1
External clock B (TCLKB)
1
0
External clock C (TCLKC)
1
External clock D (TCLKD)
10.2.10 Timer I/O Control Register (TIOR)
The timer I/O control register (TIOR) is an eight-bit read/write register that selects the output
compare or input capture function for the general registers GRA and GRB. It also selects the
function of the TIOCA and TIOCB pins. If output compare is selected, the TIOR also selects the
output settings. If input capture is selected, the TIOR also select the input capture edges. TIOR is
initialized to H'88 or H'08 on a reset or standby mode. Each ITU channel has one TIOR (table
10.8).
Table 10.8 Timer I/O Control Register (TIOR)
Abbre-
Channel viation
0
TIOR0
1
TIOR1
2
TIOR2
3
TIOR3
4
TIOR4
Function
The TIOR controls the GRs. Some functions vary during PWM. When
channels 3 and 4 are set for complementary PWM mode/reset-synchronized
PWM mode, TIOR3 and TIOR4 settings are not valid.
Bit: 7
6
5
4
3
2
1
0
Bit name: —
IOB2 IOB1 IOB0
—
IOA2 IOA1 IOA0
Initial value:
*
0
0
0
1
0
0
0
R/W: —
R/W R/W R/W
—
R/W R/W R/W
Note: Undefined
• Bit 7 (reserved): Bit 7 is read as undefined. The write value should be 0 or 1.
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