SH7020 Datasheet, PDF (95/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Module bus
Bus
interface
BBR
BAMRH
BAMRL
BARH
BARL
Break condition comparator
UBC
User break
interrupt
generating
circuit
Interrupt request
Interrupt controller
BARH, BARL: Break address registers H and L
BAMRH, BAMRL: Break address mask registers H and L
BBR: Break bus cycle register
Figure 6.1 Block Diagram of the User Break Controller
6.1.3 Register Configuration
The user break controller has five registers as listed in table 6.1. These registers are used for
setting break conditions.
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