SH7020 Datasheet, PDF (92/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

5.5 Interrupt Response Time
Table 5.5 indicates the interrupt response time, which is the time from the occurrence of an
interrupt request until the interrupt exception processing starts and fetching of the first instruction
of the interrupt service routine begins. Figure 5.4 shows the pipeline when an IRQ interrupt is
accepted.
Table 5.5 Interrupt Response Time
Number of States
Item
NMI or On-Chip
Interrupt
IRQ
Notes
Interrupt priority decision 2
3
and comparison with SR
mask bit
Wait for completion of X (≥ 0)
sequence currently being
executed by CPU
The longest sequence is the
interrupt or address error
exception processing
sequence: X = 4 + m1 + m2
+ m3 + m4. If an interrupt-
masking instruction follows,
however, the time may be
longer.
Time from interrupt
exception processing
(saving PC and SR and
fetching vector address)
until fetching of first
instruction of interrupt
service routine starts
5 + m1 + m2 + m3
Interrupt
response
Total
7 + m1 + m2 + m3 8 + m1 + m2 + m3
Minimum 10
11
0.50–0.55 µs at 20 MHz
Maximum 11 + 2(m1 + m2 + 12 + 2(m1 + m2 + (m1 = m2 = m3 = m4) 0.90–
m3) + m4
m3) + m4
0.95 µs at 20 MHz
Notes: m1–m4 are the number of states needed for the following memory accesses:
m1: SR save cycle (long word write)
m2: PC save cycle (long word write)
m3: Vector address read cycle (long word read)
m4: Fetch top instruction of interrupt service routine
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