SH7020 Datasheet, PDF (240/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 10.3 Register Configuration (cont)
Channel Name
Abbrevi-
ation
R/W
Initial
Value
Access
Address*¹ Size
4 (cont) Timer counter 4
TCNT4H R/W H'00
H'5FFFF36 8, 16
H'5FFFF37 8, 16
General register A4
GRA4H R/W H'FF
H'5FFFF38 8, 16, 32
H'5FFFF39 8, 16, 32
General register B4
GRB4H R/W H'FF
H'5FFFF3A 8, 16, 32
H'5FFFF3B 8, 16, 32
Buffer register A4
BRA4H R/W H'FF
H'5FFFF3C 8, 16, 32
H'5FFFF3D 8, 16, 32
Buffer register B4
BRB4H R/W H'FF
H'5FFFF3E 8, 16, 32
H'5FFFF3F 8, 16, 32
Notes: 1. Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Description of Areas.
2. Write 0 to clear flags.
10.2 ITU Register Descriptions
10.2.1 Timer Start Register (TSTR)
The timer start register (TSTR) is an eight-bit read/write register that starts and stops the timer
counters (TCNT) of channels 0–4. TSTR is initialized to H'E0 or H'60 upon reset or standby
mode.
Bit: 7
6
5
4
3
2
1
0
Bit name: —
—
—
STR4 STR3 STR2 STR1 STR0
Initial value:
*
1
1
0
0
0
0
0
R/W: —
—
—
R/W R/W R/W R/W R/W
Note: Undefined
• Bits 7–5 (reserved): Cannot be modified. Bit 7 is read as undefined. Bits 6 and 5 are always
read as 1. The write value to bit 7 should be 0 or 1, and the write value to bits 6 and 5 should
always be 1.
224 RENESAS