SH7020 Datasheet, PDF (20/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

A.2.2 Bit Rate Register (BRR)....................................................................................... 510
A.2.3 Serial Control Register (SCR).............................................................................. 510
A.2.4 Transmit Data Register (TDR) ............................................................................. 512
A.2.5 Serial Status Register (SSR)................................................................................. 512
A.2.6 Receive Data Register (RDR) .............................................................................. 514
A.2.7 Timer Start Register (TSTR)................................................................................ 515
A.2.8 Timer Synchronization Register (TSNC)............................................................. 515
A.2.9 Timer Mode Register (TMDR) ............................................................................ 517
A.2.10 Timer Function Control Register (TFCR)............................................................ 518
A.2.11 Timer Control Registers 0–4 (TCR0–TCR4) ....................................................... 519
A.2.12 Timer I/O Control Registers 0–4 (TIO0–TIO4)................................................... 520
A.2.13 Timer Interrupt Enable Registers 0–4 (TIER0–TIER4)....................................... 521
A.2.14 Timer Status Registers 0–4 (TSR0–TSR4) .......................................................... 522
A.2.15 Timer Counter 0–4 (TCNT0–TCNT4)................................................................. 523
A.2.16 General Registers A0–4 (GRA0–GRA4) ............................................................. 524
A.2.17 General Registers B0–4 (GRB0–GRB4).............................................................. 525
A.2.18 Buffer Registers A3, A4 (BRA3, BRA4)............................................................. 526
A.2.19 Buffer registers B3, B4 (BRB3, BRB4) ............................................................... 527
A.2.20 Timer Output Control Register (TOCR) .............................................................. 528
A.2.21 DMA Source Address Registers 0–3 (SAR0–SAR3) .......................................... 529
A.2.22 DMA Destination Address Registers 0–3 (DAR0–DAR3).................................. 530
A.2.23 DMA Transfer Count Registers 0–3 (TCR0–TCR3) ........................................... 531
A.2.24 DMA Channel Control Registers 0–3 (CHCR0–CHCR3)................................... 532
A.2.25 DMA Operation Registers (DMAOR) ................................................................. 535
A.2.26 Interrupt Priority Setting Register A (IPRA)........................................................ 536
A.2.27 Interrupt Priority Setting Register B (IPRB)........................................................ 537
A.2.28 Interrupt Priority Setting Register C (IPRC)........................................................ 538
A.2.29 Interrupt Priority Setting Register D (IPRD)........................................................ 539
A.2.30 Interrupt Priority Setting Register E (IPRE) ........................................................ 540
A.2.31 Interrupt Control Register (ICR) .......................................................................... 541
A.2.32 Break Address Register H (BARH) ..................................................................... 542
A.2.33 Break Address Register L (BARL) ...................................................................... 543
A.2.34 Break Address Mask Register H (BAMRH)........................................................ 544
A.2.35 Break Address Mask Register L (BAMRL)......................................................... 545
A.2.36 Break Bus Cycle Register (BBR) ......................................................................... 546
A.2.37 Bus Control Register (BCR) ................................................................................ 548
A.2.38 Wait State Control Register 1 (WCR1)................................................................ 549
A.2.39 Wait State Control Register 2 (WCR2)................................................................ 550
A.2.40 Wait State Control Register 3 (WCR3)................................................................ 552
A.2.41 DRAM Area Control Register (DCR).................................................................. 553
A.2.42 Parity Control Register (PCR).............................................................................. 555
A.2.43 Refresh Control Register (RCR) .......................................................................... 556
A.2.44 Refresh Timer Control/Status Register (RSTCR) ................................................ 557