SH7020 Datasheet, PDF (264/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

TCNT value
GR
H'0000
Counter cleared by
GR compare match
Time
STR0–STR4
IMF
Figure 10.16 Periodic Counter Operation
• TCNT counter timing
Internal clock source: Bits TPSC2–TPSC0 in the TCR select the system clock (CK) or one of
three internal clock sources (φ/2, φ/4, φ/8) obtained by prescaling the system clock. Figure
10.17 shows the timing.
External clock source: The external clock input pin (TCLKA–TCLKD) source is selected by
bits TPSC2–TPSC0 in the TCR and its valid edges are selected with the CKEG1 and CKEG0
bits of the TCR. The rising edge, falling edge, or both edges can be selected. The pulse width
of the external clock signal must be at least 1.5 system clocks when a single edge is selected
and at least 2.5 system clocks when both edges are selected. Shorter pulses will not be counted
correctly. Figure 10.18 shows the timing when both edges are detected.
CK
Internal clock
TCNT input
clock
TCNT value N – 1
N
Figure 10.17 Count Timing for Internal Clock Sources
N+1
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