SH7020 Datasheet, PDF (71/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 4.3 Calculation of Exception Vector table Addresses
Exception Source
Calculation of Vector table Addresses
Reset
(Vector table address) = (vector table address offset) =
(vector number) × 4
Address error, interrupt, instructions (Vector table address) = VBR + (vector table address offset)
= VBR + (vector number) × 4
Note: VBR: Vector base register. For vector table address offsets and vector numbers, see table
4.2.
4.2 Reset
4.2.1 Reset Types
A reset is the highest-priority exception. There are two types of reset: power-on reset and manual
reset. As table 4.4 shows, a power-on reset initializes the internal state of the CPU and all registers
of the on-chip peripheral modules. A manual reset initializes the internal state of the CPU and all
registers of the on-chip peripheral modules except the bus state controller (BSC), pin function
controller (PFC) and I/O ports (I/O).
Table 4.4 Reset Types
Reset
Power-on Reset
Manual Reset
Transition Conditions
NMI
RES
High
Low
Low
Low
CPU
Initialize
Initialize
Internal State
On-Chip Peripheral Module
Initialize
Initialize all except BSC, PFC and I/O
4.2.2 Power-On Reset
When the NMI pin is high, a low input at the RES pin drives the chip into the power-on reset state.
The RES pin should be driven low while the clock pulse generator (CPG) is stopped (or while the
CPG is operating during the oscillation settling time) for at least 20 t_cyc to assure that the LSI is
reset. A power-on reset initializes the internal state of the CPU and all registers of the on-chip
peripheral modules. For pin states in the power-on reset state, see appendix B, Pin States.
While the NMI pin remains high, if the RES pin is held low for a certain time then driven high in
the power-on state, power-on reset exception processing begins. The CPU then:
1. Reads the start address (initial PC value) from the exception vector table.
2. Reads the initial stack pointer value (SP) from the exception vector table.
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