SH7020 Datasheet, PDF (142/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Area 5: Area 5 is the area where addresses A26–A24 are 101 and its address range is H'5000000–
H'5FFFFFF and H'D000000–H'DFFFFFF. Figure 8.8 is a memory map of area 5.
Area 5 is allocated to on-chip peripheral module space when the A27 address bit is 0 and external
memory space when A27 is 1. In on-chip peripheral module space, bits A23–A9 are ignored and
the shadows are in 512-byte units. The bus width is 8 bits when the A8 bit is 0 and 16 bits when
A8 is 1. When on-chip peripheral module space is accessed, the CS5 signal is not valid. In
external memory space, the A23 and A22 bits are not output and the shadow is in 4-Mbyte units.
The bus width is always 16 bits. When external memory space is accessed, the CS5 signal is valid.
Logical address
space
H'5000000
H'50001FF ^Shadow
Shadow
Shadow
Logical address
space
H'D000000
Shadow
H'D3FFFFF
H'D400000
Actual
space
Shadow
Shadow
H'5FFFE00
H'5FFFFFF
Shadow
8 or 16-bit
space
Actual
space
Shadow
On chip
peripheral
module space
(512 bytes)
H'D7FFFFF
H'D800000
Shadow
A8 = 0:
8-bit space
H'DBFFFFF
H'DC00000
A8 = 1: 16-bit space*
• Ignored
addresses:
Shadow
A23–A9
(Valid addresses H'DFFFFFF
A8–A0)
16-bit space
• CS5 not valid
External
memory
space
(4 Mbytes)
• Valid
addresses
A21–A0
A23 and A22
not output)
• CS5 valid
Note: Some registers in onchip peripheral modules can only be accessed as 8-bit registers
even though they occupy 16 bits (see Appendix A).
Figure 8.8 Memory Map of Area 5
Area 6: Area 6 is the area where addresses A26–A24 are 110 and its address range is H'6000000–
H'6FFFFFF and H'E000000–H'EFFFFFF. Figure 8.9 is a memory map of area 6.
124 RENESAS