SH7020 Datasheet, PDF (324/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bit: 7
6
5
4
3
2
1
0
Bit name: PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Note: Bits set to TPC output by NDERA or NDERB are read-only.
11.2.3 Next Data Register A (NDRA)
NDRA is an eight-bit read/write register that stores the next output data for TPC output groups 1
and 0 (TP7–TP0). When used for TPC output, the contents of the NDRA are transferred to the
corresponding PBDR bits when the ITU compare match specified in the TPC output control
register TPCR occurs.
The address of the NDRA differs depending on whether TPCR settings select the same trigger or
different triggers for TPC output groups 1 and 0. When reset, NDRA is initialized to H'00. It is not
initialized by standby mode.
Same Trigger for TPC Output Groups 1 and 0: If TPC output groups 1 and 0 are triggered by
the same compare match, the address of the NDRA is H'FFFFF5. The 4 upper bits becomes group
1 and the 4 lower bits become group 0. Address H'5FFFFF7 in such cases consists entirely of
reserved bits. These bits cannot be modified and always read as 1.
Address H'5FFFFF5:
• Bits 7–4 (next data 7–4 (NDR7–NDR4)): NDR7-NDR4 store the next output data for TPC
output group 1.
• Bits 3–0 (next data 3–0 (NDR3–NDR0)): NDR3-NDR0 store the next output data for TPC
output group 0.
Bit:
Bit name:
Initial value:
R/W:
7
NDR7
0
R/W
6
NDR6
0
R/W
5
NDR5
0
R/W
4
NDR4
0
R/W
3
NDR3
0
R/W
2
NDR2
0
R/W
1
NDR1
0
R/W
0
NDR0
0
R/W
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