SH7020 Datasheet, PDF (123/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bit:
Bit name:
Initial value:
R/W:
15
CW2
0
R/W
14
RASD
0
R/W
13
TPC
0
R/W
12
11
10
9
8
BE CDTY MXE MXC1 MXC0
0
0
0
0
0
R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Bit name: —
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: —
—
—
—
—
—
—
—
• Bit 15 (dual-CAS or dual-WE select bit (CW2)): When accessing a 16-bit bus width space,
CW2 selects the dual-CAS or the dual-WE method. When cleared to 0, the CASH, CASL, and
WRL signals are valid ; when set to 1, the CASL, WRH, and WRL signals are valid. When
accessing an 8-bit space, only CASL and WRL signals are valid, regardless of CW2 settings.
Bit 15L: CW2
0
1
Description
Dual-CAS: CASH, CASL, and WRL signals are valid (initial value)
Dual-WE: CASL, WRH, and WRL signals are valid
• Bit 14 (RAS down (RASD)): When DRAM access pauses, RASD determines whether to keep
RAS low while waiting for the next DRAM access (RAS down mode) or return it to high
(RAS up mode). When cleared to 0, the RAS signal returns to high; when set to 1, it stays at
low.
Bit 14: RASD
0
1
Description
RAS up mode: Return RAS signal to high and wait for the next DRAM
access (initial value)
RAS down mode: Keep RAS signal low and wait for the next DRAM
access
• Bit 13 (RAS precharge cycle count (TPC)): TPC selects whether the RAS signal precharge
cycle (T_P) will be 1 state or 2. When TPC is cleared to 0, a 1-state precharge cycle is inserted;
when 1 is set, a 2-state precharge cycle is inserted.
Bit 13: TPC
0
1
Description
Inserts 1-state precharge cycle (initial value)
Inserts 2-state precharge cycle
RENESAS 105