SH7020 Datasheet, PDF (158/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

When the RW1 bit is set to 1, the number of wait states selected by CBR refresh wait state
insertion bits 1 and 0 (RLW1, RLW0) of the refresh control register (RCR) are inserted into the
CAS-before-RAS refresh cycle.
8.5.4 Byte Access Control
16-bit width and 18-bit width DRAMs require different types of byte control signals for access. By
setting the dual CAS signals/dual WE signals select bit (CW2) in the DCR, the BSC allows
selection of either the dual CAS signals or the dual WE signals system of control signals. When
16-bit space is being accessed and the CW2 bit is cleared to 0 for dual CAS signals, CASH,
CASL, and WRL signals are output; when CW2 is set to 1 for dual WE signals, the CASL, WRH,
and WRL signals are output. When accessing 8-bit space, WRL and CASL are output regardless
of the CW2 setting.
Figure 8.21 shows the control timing of the upper byte write cycle (short pitch) in 16-bit space.
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