SH7020 Datasheet, PDF (332/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bit 0: G0NOV
0
1
Description
TPC output group 0 operates normally (output value updated according
to compare-match A of the ITU channel selected by TPCR) (initial
value)
TPC output group 0 operates in non-overlap mode (1 output and 0
output can be performed independently according to compare-match A
and B of the ITU channel selected by TPCR)
11.3 Operation
11.3.1 Overview
When corresponding bits in the PBCR1, PBCR2, NDERA and NDERB registers are set to 1, TPC
output is enabled and the PBDR data register values are output. After that, when the compare-
match event selected by TPCR occurs, the next data register contents (NDRA and NDRB) are
transferred to the PBDR and output values are updated. Figure 11.2 illustrates the TPC output
operation.
CR
NDER
Q
Q
Output trigger
signal
TPC
output pin
Port function
select
C
Q DR D
Q NDR D
Internal
data bus
Figure 11.2 TPC Output Operation
If new data is written in next data registers A and B before the next compare-match occurs, a
maximum 16 bits of data can be output at each successive compare-match. See section 11.3.4,
TPC Output Non-Overlap Operation, for details on non-overlap operation.
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