SH7020 Datasheet, PDF (167/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

refresh will not be performed until the RTCNT again matches the RTCOR value, the initial refresh
interval will be rather long. It is thus advisable to set the RTCOR cycle prior to setting the CKS2–
CKS0 bits and start it incrementing. When CBR refresh control is being performed after its use as
an 8-bit interval timer, the RTCNT count value may be in excess of the refresh cycle. For this
reason, clear the RTCNT by writing H'00 before starting refresh control to assure a correct refresh
interval.
When the RW1 bit of WCR1 is set to 1 and the read cycle is set to long pitch, the number of wait
states selected by the RLW1 and RLW0 bits of the RCR will be inserted into the CBR refresh
cycle, regardless of the status of the WAIT signal. Figure 8.29 shows the RTCNT operation and
figure 8.30 shows the timing of the CBR refresh. For details on timing, see section 20.3.3, Bus
Timing.
RTCNT
value
RTCOR
value
Compare
match
with RTCOR
Compare
match
with RTCOR
Compare
Compare
match
match
with RTCOR with RTCOR
H'00
Clock
CBR
selected with
CKS2–CKS0
CBR
CBR
CBR: CAS-before-RAS refresh
CBR
Figure 8.29 Refresh Timer Counter (RTCNT) Operation
Time
CK
RAS
CAS
T_Rp
T_Rr
T_Rc
Figure 8.30 Output Timing for CAS-Before-RAS Refresh Signal
Self-Refresh Mode: Some DRAMs have a self-refresh mode (parity back-up mode). This is a
type of a standby mode in which the refresh timing and refresh addresses are generated inside the
DRAM chip. When the RFSHE and RMODE bits of the RCR are both set to 1, the DRAM will
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