SH7020 Datasheet, PDF (248/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

• Bit 1 (output level select 4 (OLS4)): OLS4 selects the output level of the complementary PWM
mode or reset-synchronized PWM mode.
Bit 1: OLS4
0
1
Description
TIOCA3, TIOCA4, and TIOCB4 are inverted and output
TIOCA3, TIOCA4, and TIOCB4 are output directly (initial value)
• Bit 0 (output level select 3 (OLS3)): OLS3 selects the output level of the complementary PWM
mode or reset-synchronized PWM mode.
Bit 0: OLS3
0
1
Description
TIOCB3, TOCXA4, and TOCXB4 are inverted and output
TIOCB3, TOCXA4, and TOCXB4 are output directly (initial value)
10.2.6 Timer Counters (TCNT)
The ITU has five 16-bit timer counters (TCNT), one for each channel (table 10.4).
Each TCNT is a 16-bit read/write counter that counts by input from a clock source. The clock
source is selected by timer prescalar bits 2–0 (TPSC2–TPSC0) in the timer control register (TCR).
TCNT0 and TCNT 1 are strictly upcounters. Up/down counting occurs for TCNT2 when the phase
counting mode is selected, or for TCNT3 and TCNT 4 when complementary PWM mode is
selected. In other modes, they are upcounters.
The TCNT can be cleared to H'0000 by compare match with the corresponding general register A
or B (GRA, GRB) or input capture to GRA or GRB (counter clear function).
When the TCNT overflows (changes from H'FFFF–H'0000), the overflow flag (OVF) in the timer
status register (TSR) is set to 1. The OVF of the corresponding channel TSR is also set to 1 when
the TCNT underflows (changes from H'0000–H'FFFF).
The TCNT is connected to the CPU by a 16-bit bus, so it can be written or read by either word
access or byte access. The TCNT is initialized to H'0000 by a reset or in standby mode.
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