SH7020 Datasheet, PDF (182/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

The countermeasures are not required when DRAM data is initialized or loaded again after manual
reset.
8.11.2 Usage Notes on Parity Data Pins DPH and DPL
The following specifies the setup time tDS of the parity dada DPH and DPL to CAS signal rising
when the parity dada DPH and DPL are written to DRAM in long-pitch mode (early write).
Table 8.12 Setup Time of Parity Data DPH and DPL
Item
Data setup time to CAS
(for only DPH and DPL in long-pitch mode)
Symbol
tDS
min
–5 ns
Therefore, when writing parity data DPH and DPL to the DRAM in long-pitch mode, delay the
WRH and WRL signals of this LSI and write with delayed writing.
Nomal dada is also delayed-written, causing no problems.
SuperH RAS
Microcomputer CAS
RD
WRH or WRL
CK
*1 *1
DQ
*2 _Q
DWRH or DWRL
RAS
CAS
OE
WE
DRAM
*1: For preventing signal racing
*2: Negative edge latch
Figure 8.42 Delayed-Write Control Circuit
8.11.3 Maximum Number of States from BREQ Input to Bus Release
The maximum number of states from BREQ input to bus release is:
Maximum number of states for which bus is not released + approx. 4.5 states
Note:
Breakdown of approx. 4.5 states:
1.5 states:
Until BACK output after end of bus cycle
1 state (min.): tBACD1
1 state (max.): tBRQS
1 state:
Sampling in 1 state before end of bus cycle
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