SH7020 Datasheet, PDF (357/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

13.1.2 Block Diagram
Figure 13.1 shows a block diagram of the SCI.
Module data bus
RXD
TXD
SCK
RDR
RSR
TDR
SSR
BRR
SCR
TSR
SMR
Transmit/
receive control
Baud rate
generator
Parity
generation
Clock
Parity check
External clock
SCI
RSR: Receive shift register
RDR: Receive data register
TSR: Transmit shift register
TDR: Transmit data register
SMR: Serial mode register
SCR: Serial control register
SSR: Serial status register
BRR: Bit rate register
Figure 13.1 SCI Block Diagram
Internal
data bus
φ
φ/4
φ/16
φ/64
TEI
TXI
RXI
ERI
RENESAS 342